The present invention relates to a static RAM (random access memory) integrated circuit of high memory density. More particularly, it relates to a fast-access RAM which, in reading out stored data from a memory cell, changes a data bus line load in correspondence with the data to be read out, thereby realizing fast read-out.
When it is intended to make the memory density of a static RAM high, the size of each cell for storing data becomes small. Since the cell of the ordinary static RAM is constructed of a flip-flop circuit, the small cell size results in lowering the transconductances g.sub.m of MIS field effect transistors (hereinbelow, termed "MOS FETs") for a cell driver. In order to attain the function of the memory cell satisfactorily (that is, to cause the transistor on the "ON" side of the cell to pull down the corresponding bit line), current which flows through a load for pulling up the bit line must be reduced. By way of example, when a MOS FET is used as the load, its transconductance g.sub.m must be made small. This causes degradation in the charging ability of the bit line, that is, lowering in the changing rate thereof from a low level to a high level, so that the rise of the potential of the bit line becomes slow. Under such a condition, it is difficult to make the operation of the high-density static RAM fast.